SPARC V8 Testing board
Description
This board was developed for performing radiation-hardness testing of SPARC V8 processor. There is 16 MBit static RAM and 256 MBit Flash ROM with error correction mechanism, ethernet controller, and auxilliary MCU for controlling testing process. Testing program loaded to Flash ROM through ethernet debug interface. It performs cyclic internal RAM testing and onchip UART interface testing. Results sent to auxiliarry MCU through parallel GPIO bus and than MCU send result to PC by RS-232 interface.
Schematic
PCB layout